library IEEE ;
use IEEE.STD_LOGIC_1164.ALL ;
use IEEE.STD_LOGIC_ARITH.ALL ;
use IEEE.STD_LOGIC_UNSIGNED.ALL ;
use WORK.ALL ;

entity ir_receiver is
    Port (   IRin : in std_logic ;
          Clk : in std_logic ;
          INT : out std_logic ;
          Dout : out std_logic_vector ( 7 downto 0 ) ) ;
end ir_receiver ;

architecture beh of ir_receiver is
    signal ir_new : std_logic := '0' ;
    signal ir_old : std_logic := '0' ;
    signal last_level : std_logic := '0' ;
    signal latch_ctr_old : std_logic := '0' ;
    signal ir_change, latch_ctr : std_logic ;
    signal endval : std_logic ;

    component cntreg7
    port(
        CCnt : IN std_logic ;
        CReg : IN std_logic ;
        R : IN std_logic ;
        Q : OUT std_logic_vector ( 6 downto 0 ) ;
        EndVal : OUT std_logic ) ;
    end component ;

begin

    -- make input synchronous and store old input-level
    sync : process( Clk )
    begin
        if ( Clk'event and Clk='1' ) then
            ir_new <= IRin ;
            ir_old <= ir_new ;
            latch_ctr_old <= latch_ctr ;
        end if ;
    end process sync ;

    -- save last level of ir-receiver
    level : process( latch_ctr )
    begin
        if ( latch_ctr'event and latch_ctr='1' ) then
            last_level <= ir_old ;
        end if ;
    end process level ;

    -- interrupt
    INT <= latch_ctr and not latch_ctr_old ;

    -- other control signals
    ir_change <= '1' when ir_old /= ir_new else '0' ;
    latch_ctr <= ir_change or endval ;
    Dout( 7 ) <= last_level ;

    -- count-register
    countreg: cntreg7
    port map(
      CCnt => Clk,
      CReg => latch_ctr,
      R => ir_change,
      Q => Dout( 6 downto 0 ),
      EndVal => endval
    ) ;

end beh ;



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