library IEEE ;
use IEEE.STD_LOGIC_1164.ALL ;
use IEEE.STD_LOGIC_ARITH.ALL ;
use IEEE.STD_LOGIC_UNSIGNED.ALL ;

entity idectrl is
    Port (   nCS : in std_logic ;
          nWR : in std_logic ;
          nRD : in std_logic ;
          A : in std_logic_vector ( 4 downto 0 ) ;
          Din : in std_logic_vector ( 7 downto 0 ) ;
          Dout : out std_logic_vector ( 7 downto 0 ) ;
          INT : out std_logic ;
          IDE_nCS0 : out std_logic ;
          IDE_nCS1 : out std_logic ;
          IDE_nWR : out std_logic ;
          IDE_nRD : out std_logic ;
          IDE_A : out std_logic_vector ( 2 downto 0 ) ;
          IDE_D : inout std_logic_vector ( 15 downto 0 ) ;
          IDE_INT : in std_logic ) ;
end idectrl ;

architecture beh of idectrl is
    signal RD_Latch : std_logic_vector ( 7 downto 0 ) := "00000000" ;
    signal WR_Latch : std_logic_vector ( 7 downto 0 ) := "00000000" ;
    signal IDE_D_Buf : std_logic_vector ( 15 downto 0 ) ;
    signal reading_bus, writing_bus : std_logic ;
    signal reading_latch, writing_latch : std_logic ;
begin

    -- read or write operation in progress
    reading_bus <= '1' when ( nCS='0' and nRD='0' and A( 0 )='0' ) else '0' ;
    writing_bus <= '1' when ( nCS='0' and nWR='0' and A( 0 )='1' ) else '0' ;
    reading_latch <= '1' when ( nCS='0' and nRD='0' and A( 0 )='1' ) else '0' ;
    writing_latch <= '1' when ( nCS='0' and nWR='0' and A( 0 )='0' ) else '0' ;

    -- control signals of IDE bus
    IDE_A <= A( 3 downto 1 ) ;
    IDE_nCS0 <= '0' when ( nCS='0' and A( 4 )='0' ) else '1' ;
    IDE_nCS1 <= '0' when ( nCS='0' and A( 4 )='1' ) else '1' ;
    IDE_nWR <= not writing_bus ;
    IDE_nRD <= not reading_bus ;
    INT <= IDE_INT ;

    -- IDE data bus
    IDE_D_Buf( 15 downto 8 ) <= Din ;
    IDE_D_Buf( 7 downto 0 ) <= WR_Latch ;
    IDE_D <= IDE_D_Buf when writing_bus='1' else "ZZZZZZZZZZZZZZZZ" ;

    -- internal data out
    Dout <= IDE_D( 7 downto 0 ) when A( 0 )='0' else RD_Latch ;

    -- write latch
    write_latch: process( writing_latch, Din )
    begin
        if ( writing_latch='1' ) then
          WR_Latch <= Din ;
      end if ;
    end process write_latch ;

    -- read latch
    read_latch: process( reading_bus, IDE_D( 15 downto 8 ) )
    begin
        if ( reading_bus='1' ) then
          RD_Latch <= IDE_D( 15 downto 8 ) ;
      end if ;
    end process read_latch ;

end beh ;



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