library IEEE ;
use IEEE.STD_LOGIC_1164.ALL ;
use IEEE.STD_LOGIC_ARITH.ALL ;
use IEEE.STD_LOGIC_UNSIGNED.ALL ;

entity DecodeDemux is
    Port (   nCE : in std_logic ;
          Abus : in std_logic_vector ( 5 downto 0 ) ;
          Aint : out std_logic_vector ( 5 downto 0 ) ;
          Dbusout : out std_logic_vector ( 7 downto 0 ) ;
          nCElcd : out std_logic ;
          nCEide : out std_logic ;
          nCEkey : out std_logic ;
          nCEir : out std_logic ;
          nCEposenc : out std_logic ;
          Dlcd : in std_logic_vector ( 7 downto 0 ) ;
          Dide : in std_logic_vector ( 7 downto 0 ) ;
          Dkey : in std_logic_vector ( 7 downto 0 ) ;
          Dir : in std_logic_vector ( 7 downto 0 ) ;
          Dposenc : in std_logic_vector ( 7 downto 0 ) ) ;
end DecodeDemux ;

architecture Beh of DecodeDemux is

signal A : std_logic_vector ( 5 downto 0 ) ;

begin

    -- Decoder
    nCEide <= '0' when ( nCE='0' and A( 5 )='0' ) else '1' ;
    nCElcd <= '0' when ( nCE='0' and A( 5 downto 3 )="100" ) else '1' ;
    nCEir <= '0' when ( nCE='0' and A( 5 downto 3 )="101" ) else '1' ;
    nCEkey <= '0' when ( nCE='0' and A( 5 downto 3 )="110" ) else '1' ;
    nCEposenc <= '0' when ( nCE='0' and A( 5 downto 3 )="111" ) else '1' ;

    -- Demux
    Dbusout <= Dide when A( 5 )='0' else
              Dlcd when A( 4 downto 3 )="00" else
              Dir when A( 4 downto 3 )="01" else
              Dkey when A( 4 downto 3 )="10" else
              Dposenc ;

    -- Address-Gate
    A <= Abus when nCE='0' else "111111" ;
    Aint <= A ;

end Beh ;



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